FIG. 1 is a schematic block diagram of a portion of a conventional memory-cell array 100 for a dynamic random access memory (DRAM). The memory-cell array 100 includes a number of memory cells 102 arranged in rows and columns, each memory cell including an access switch in the form of an NMOS transistor 104 and a storage element in the form of a capacitor 106. The capacitor 106 includes a first plate that receives a reference potential which is typically equal to approximately a supply voltage Vdd divided by two (Vdd/2), with the first plate typically being common to the first plates of all other capacitors in the array 100. The reference potential applied to the first plate of the capacitors 106 may be any value between Vdd and ground or another a low reference supply Vss, as will be appreciated by those skilled in the art. A second plate of the capacitor 106 is coupled to the drain of the transistor 104. Each of the memory cells 102 stores a single bit of binary data in the form of a voltage across the capacitor 106. A voltage of approximately Vdd at the second plate of the capacitor 106 corresponds to a first binary data value and a voltage of approximately zero volts at the second plate corresponds to a second binary data value.
The memory cells 102 are arranged in n rows and m columns, with one memory cell positioned at the intersection of each row and column. Each row of memory cells 102 has an associated word line WL0-WLN-1 and each column of memory cells has an associated pair of true and complementary bit lines BL0, BL0*-BLM-1, BLM-1*, where the bit “*” indicates that data on the complementary bit line is the complement of data on the associated true bit line, as will be appreciated by those skilled in the art. The bit lines may be referred to generally as BL, BL* and the word lines as WL in the following description. Each memory cell 102 in a given row of memory cells has a control terminal in the form of the gate of the transistor 104 coupled to the associated word line WL0-WLN-1 and each memory cell in a given column of memory cells has a data terminal in the form of the source terminal of the transistor 104 coupled to one of the associated complementary bit lines BL0, BL0*-BLM-1, BLM-1*.
Each pair of bit lines BL,BL* is coupled to a corresponding sense amplifier 108 that senses and stores data in an addressed memory cell 102 coupled to one of the corresponding bit lines. In the simplified diagram of FIG. 1, each sense amplifier is assumed to include isolation transistors for selectively coupling and decoupling the sense amplifier from the corresponding bit lines BL, BL* and equilibration transistors coupled between the pair of bit lines for driving or “equilibrating” the bit lines to equal voltages when activated.
In operation of the memory-cell array 100, before data is read from the memory cells 102, control circuitry (not shown) in the DRAM executes an equilibration cycle. During the equilibration cycle, row drivers in the control circuitry drive each of the word lines WL low, thereby deactivating each of the memory cells 102. At the same time, each sense amplifier 108 equilibrates the associated bit line BL, BL* to equalize the voltage on each bit line to approximately Vdd/2. After the equilibration cycle, the row driver of the word line WL of the addressed memory cell 102 is driven with a boosted or “pumped” voltage Vpp which is greater than Vdd to activate each memory cell coupled to the activated word line. In response to the voltage VPP on activated word line WL, the transistor 104 in each activated memory cell 102 coupled to that word line is turned ON and charge is transferred between the memory cell and the associated bit line BL, BL*. For example, if the word line WL0 is activated charge is transferred between the capacitors 106 in each memory cell 102 coupled to this word line and the associated complementary bit lines BL0*, BLM-1*.
This charge transfer results in the complementary bit lines BL0*, BLM-1* either increasing slightly above or decreasing slightly below the equilibrated voltage of Vdd/2, depending on the logic state of data stored in the memory cell 102. Each sense amplifier 108 then compares the voltage on the complementary bit line BL, BL* coupled to the activated memory cell 102 to the voltage of Vdd/2 on the other bit line. In response to the sensed voltage differential between the bit lines BL, BL*, each sense amplifier 108 drives the higher bit line to approximately Vdd and drives the lower bit line to approximately zero volts. The voltage levels on each pair of bit lines BL, BL* coupled to the activated memory cells 102 now represents the binary value of the data stored in the activated memory cell in that column of memory cells. The data contents of the addressed memory cells 102 are then read from each sense amplifier 108 coupled to a column of an addressed memory cell by read/write circuitry (not shown in FIG. 1). During a write operation, data is transferred through a read/write data path (not shown) and applied to the respective bit lines BL, BL* of addressed memory cells 102, with the word line WL of the row containing the addressed memory cells being driven high to thereby couple the voltage on one of the bit lines to the capacitors 106 in the addressed memory cells 102.
As described above, the row drivers drive each word line WL with a pumped voltage Vpp that is greater than the supply voltage Vdd. This enables the storage capacitors 106 to be charged to the full supply voltage Vdd when binary data corresponding to this voltage level is to be stored in the memory cell 102. More specifically, to enable the access transistors 104 in each memory cell 102 to charge the capacitor 106 to the voltage Vdd on the associated bit line BL, BL* the voltage on the word line WL applied to the gate of that transistor must be greater than the voltage Vdd. This is true because to remain turned ON each transistor 104 must receive a gate-to-source voltage that is greater than a threshold voltage VT required to keep the transistor turned ON. This threshold voltage VT is shown for the memory cell 102 in row 0 and column 0 in the array of FIG. 1 and corresponds to the voltage between the bit line BL0* and the word line WL0. Thus, to remain turned ON to charge the capacitor 106 to Vdd, the pumped voltage Vpp on the word line WL0 must greater than the supply voltage Vdd by at least the threshold voltage VT (Vpp>Vdd+VT).
In a typical DRAM, a charge pump (not shown in FIG. 1) generates the pumped voltage Vpp from the supply voltage Vdd, as will be appreciated by those skilled in the art. In other instances, the pumped voltage Vpp is supplied to the DRAM from an external power supply. For example, an application specific integrated circuit (ASIC) is a chip designed for a specific application, and many times including a DRAM portion for data storage during operation. A typical ASIC may also include bipolar components for interfacing the ASIC to external circuitry, for example, or other components that do not operate at conventional supply voltage supplied to components in the DRAM portion. As a result, a typical ASIC receives a low supply voltage Vdd for powering circuitry in the DRAM portion and other low voltage circuitry in the ASIC and also receives a high supply voltage Vpp for powering bipolar or other higher voltage components in the ASIC.
Since the ASIC receives the voltage Vpp from an external voltage source, this higher voltage may be directly applied to the DRAM portion of the ASIC to be used in generating the pumped voltage required for driving the word lines WL in the memory-cell array 100. This high supply voltage Vpp is not typically high enough to be used directly in driving the word lines WL but instead must be boosted, albeit not by as much as if the low supply voltage Vdd was being boosted to generate the required voltage for driving the word lines WL. In this situation, two independent supply voltage sources supply voltages to the ASIC, one generating the low supply voltage Vdd and one generating the high supply voltage Vpp. These two supply voltages may vary in different ways as a function of various parameters such as time and temperature. As a result, the differential between these voltages may vary over time, resulting in a larger differential voltage between these two supply voltages Vdd and Vpp depending on how the voltage vary as function of various parameters.
High voltages across components in the memory-cell array 100 such as the NMOS transistors 104 stress these components and can thereby damage and reduce the operable life of such components. This is true, for example, because higher voltages break down oxide layers in such devices, such as the oxide layer formed between the gate and a channel region of each transistor 104. Thus, as the differential voltage between the supply voltages Vdd and Vpp increases some components in the memory-cell array 100 DRAM may be stressed due to being subjected to higher voltages. Such stress on components in the array 100 may damage and reduce the operational life of components in the DRAM, reducing the overall operational life of the ASIC.
As previously mentioned, the high supply voltage Vpp must typically be boosted to generate the required boosted voltage for the word lines WL in the array 100. This boosted voltage is typically a function of the magnitude or value of the high supply voltage Vpp and thus varies as this supply voltage varies. For example, assume the nominal value of the high supply voltage Vpp is 3.3 volts and that boost circuitry in the DRAM portion of the ASIC generates a boosted voltage of 4.2 volts when the high supply voltage equals this nominal value. Thus, in this example an incremental boost voltage of 0.9 volts (4.2 volts−3.3 volts) is added to the high supply voltage Vpp to generate the boosted voltage. This incremental boost voltage is added regardless of the value of the high supply voltage Vpp, meaning that if the high supply voltage increases to 3.6 volts the boosted voltage now equals 4.5 volts. Thus, as the supply voltage Vpp increases the boosted voltage increases due to the constant incremental boost voltage. This can result in higher than desired voltages across components in the memory-cell array, stressing such components as previously discussed and thereby reducing the overall operational life of the ASIC.
There is a need for a circuit and method of providing boosted voltages in DRAMs and other integrated circuit devices that are great enough to ensure proper operation of the devices but not too large to reduce the operational lives of such devices.